Reusable RISC-V platform device models (CLINT, 16550 UART, SYSCON) for the RISC-V-emulator family.
RISC-V-emulator-Devices
The ISA core emulates instructions. This library emulates the hardware around it: timers, serial ports and whatever else a board needs, shared across every port.
What you get
- Header-only C: `RiscvEmulatorDeviceClint.h`, `RiscvEmulatorDeviceUart16550.h`, `RiscvEmulatorDeviceSyscon.h`.
- A QEMU `virt`-compatible default memory map.
- Macro hooks for UART TX, poweroff and reboot.
- Unity tests under `test/`.
The data path
A guest store lands in the board's store hook, which offers the address to each device in turn. CLINT compares `mtime` against `mtimecmp`; the UART moves bytes through a 16-byte FIFO and reports the highest-priority interrupt in `IIR`. Reads of the low `mtime` word latch the high word, which is what Linux expects. The board supplies the clock and the `mip` bridge, so the library stays free of 64-bit division and host I/O.