RISC-V emulator

Want to understand RISC-V? Emulate it. This RV32 core in plain C runs on anything from an 8-bit AVR to x86-64 Linux, and the riscv-arch-test suite vouches for every extension it implements.

What you compile in

• One library, zero architecture dependencies.
• RV32I plus a growing extension set — pick per build via a config header of defines.
• Bring your own RAM and hook functions for loads, stores and traps.

How an instruction runs

Your program supplies RAM and keeps calling RiscvEmulatorLoop(). Inside, decoding happens in two passes: opcode first, then a nested switch() that decodes and executes. Bitfield structs and the occasional helper-struct union keep the bit shuffling readable.